1. Field of the Invention
The present invention relates generally to a method for manufacturing a field effect transistor, and more particularly, to a method for manufacturing a field effect transistor employed in a semiconductor memory device or the like which is directed toward high integration density.
2. Description of the Prior Art
FIG. 1 is a block diagram showing an example of structure of a general RAM (Random Access Memory). In FIG. 1, a memory cell array 101 has a plurality of word lines and a plurality of bit lines arranged intersecting with each other, a memory cell being provided at each of intersections of the word lines and the bit lines. The memory cell is selected on the basis of an intersection of one word line selected by an X address buffer decoder 102 and one bit line selected by a Y address buffer decoder 103. Data is written to the selected memory cell or data stored in the memory cell is read out. The writing/reading of data is designated in response to a read/write control signal (R/W) applied to an R/W control circuit 104. At the time of writing data, input data (Din) is inputted to the selected memory cell through the R/W control circuit 104. On the other hand, at the time of reading out data, the data stored in the selected memory cell is detected and then, amplified by a sense amplifier 105, to be outputted to the exterior through a data output buffer 106 as output data (Dout).
FIG. 2 is an equivalent circuit diagram of a dynamic memory cell shown for explaining a read/write operation of the memory cell.
In FIG. 2, the dynamic memory cell comprises a set of a field effect transistor 108 and a capacitor 109. A gate electrode of the field effect transistor 108 is connected to a word line 110, and source and drain electrodes are connected to the capacitor 109 and to a bit line 107, respectively. At the time of writing data, a predetermined potential is applied to the word line 110 so that the field effect transistor 108 is rendered conductive, whereby charges applied to the bit line 107 is stored in the capacitor 109. On the other hand, at the time of reading out data, a predetermined potential is applied to the word line 110 so that the field effect transistor 108 is rendered conductive, whereby the charges stored in the capacitor 109 is extracted through the bit line 107.
FIG. 3 is a plan view showing a part of the memory cell array shown in FIG. 1, and FIG. 4 is a cross sectional view taken along a line IV--IV shown in FIG. 3.
Referring now to FIGS. 3 and 4, the structure thereof will be described. A cell isolation region is formed on a semiconductor substrate 1, the cell isolation region comprising an ion diffused layer 2 of the same conductivity type as that of the substrate 1 and a thick oxide film 3. In addition, a capacitor region is formed, the capacitor region comprising an ion diffused layer 4 of a conductivity type opposite to that of the semiconductor substrate 1 for forming a direct contact, a storage node 5 formed of polysilicon (polycrystalline silicon) material or the like for storing charges and a cell plate electrode 6 formed of the polysilicon material or the like.
In addition, a transfer gate transistor region is formed, the transfer gate transistor region comprising a transfer gate electrode 7 comprising a polysilicon single layer, two-layer structure of polysilicon and refractory metal silicide or a refractory metal single layer and ion diffused layers 8 (8a, 8b, 8c) of the conductivity type opposite to that of the semiconductor substrate 1 for forming source and drain regions. An interlayer insulating film 14 of an oxide film is formed to cover the capacitor region and the transfer gate transistor region. A contact hole 9 is formed in the interlayer insulating film 14 to make contract with the ion diffused layer 8b. A bit line 10 comprising the two-layer structure of polysilicon and refractory metal or the refractory metal is formed on the interlayer insulating film 14 so as to be connected to the ion diffused layer 8b through the contact hole 9. A thin insulating film 11 comprising multilayer structure of an oxide film and a nitride film is formed between the storage node 5 and the cell plate electrode 6, and an insulating film 12 of an oxide film is formed under the transfer gate electrode 7.
Such a memory cell is generally manufactured in the order of the cell isolation region, the memory capacitor region, the transfer gate transistor region and the bit line or in the order of the cell isolation region, the transfer gate transistor region, the memory capacitor region and the bit line.
Referring now to cross sectional views of FIGS. 5A to 5C, description is made on manufacturing processes of the transfer gate transistor region.
An oxide film 12 is formed on a semiconductor substrate 1 by thermal oxidation, and a transfer gate electrode material 7m is deposited on the oxide film 12. In addition, exposure L is applied to a resist 13m on the electrode material through a photomask 15 by a photolithographic technique, as shown in FIG. 5A. Consequently, a patterned resist 13 is formed on the electrode material 7m , as shown in FIG. 5B. The exposed transfer gate electrode material 7m is etched utilizing the resist 13 as a mask, so that a transfer gate electrode 7 is formed, as shown in FIG. 5C.
Ions I of a conductivity type opposite to that of the semiconductor substrate 1 are implanted utilizing the transfer gate electrode 7 as a mask, and ion diffused layers 8 of the conductivity type opposite to that of the semiconductor substrate 1 serving as a drain and a source are formed by heat treatment, as shown in FIG. 5D. In the foregoing processes, a transfer gate transistor is manufactured.
The above described method for manufacturing the transfer gate transistor in the conventional memory cell has the following problem.
The ions of the conductivity type opposite to that of the semiconductor substrate 1 are implanted utilizing the transfer gate electrode 7 as a mask, and the ion diffused layers 8 of the conductivity type opposite to that of the semiconductor substrate 1 serving as a drain and a source are formed by heat treatment.
However, the direction of diffusion of ions implanted into the semiconductor substrate 1 at the time of heat treatment includes not only the direction perpendicular to the surface of the semiconductor substrate 1 but also the direction parallel thereto. Thus, the implanted ions are naturally diffused under the transfer gate electrode 7.
As a result, a channel region under the transfer gate electrode 7 becomes narrow, so that an effective gate length (a channel length represented by L) of a transfer gate is decreased. On the other hand, as integration density of the semiconductor device is increased, the length of the transfer gate is decreased, so that a short channel effect such as the drop in threshold voltage, the drop in breakdown voltage between the source and the drain, and degradation of characteristics of the transfer gate transistor caused by a hot carrier effect becomes a serious problem. In such a background of the semiconductor device which is being made fine, the decrease in the effective gate length in the conventional method for manufacturing the transfer gate enhances the above described short channel effect, which is undesirable.
In order to avoid the above described problem, a method of previously calculating the length of the ion diffused layer 8 expanding below the gate electrode 7 and forming the gate electrode 7 having a length including the calculated length is considered. However, this method presents the following new problem.
As shown in FIG. 4, the gate electrode 7 must be formed not to come into contact with the storage node 5 and the contact hole 9. However, the position where the gate electrode 7 is formed depends on the position where the resist 13 is formed, i.e., the position where the photomask 15 is located, as shown in FIGS. 5A and 5B. Thus, in consideration of an error of mask alignment (represented by S) based on the mechanical attachment precision, there is provided margin for the dimension of the position where the gate electrode 7 or the like is formed. Consequently, formation of the gate electrode 7 which is larger than necessary leads to the decrease in this margin. On the other hand, if it is desired to ensure the margin without any decrease, the distance between the central position of the gate electrode 7 and the storage node 5 or the like is increased, which is disadvantageous to a high integration density of the device.